Developing an underpowered ASIC with a RISC-V and a couple of cores
(i.e. underpowered because no FLASH, limited RAM, limited peripherals)
really doesn't bring anything to the table in terms of a usable finished
product. Seems like more of a test platform. SiFive's business model is
that they can provide RISC-V cores for integration into a larger ASIC,
and the chip they developed is a test platform for demonstrating that
capability I believe. I'm not quite sure I understand SiFive's model
for making money though ... I think it *might* be as a consulting firm
to help companies develop custom extensions to the RISC-V ISA / core for
specialized hardware acceleration, etc.
Post by franck gastel ***@gmail.com [nuttx]
again I do not get the goal of making an asic out of a risc + a couple
of cores. what does it bring ?
This would be the first RISC-V chip developed by SiFive I
believe. SiFive was founded by the guys from Berkley who created
the RISC-V. I have been working with them on the RISC-V debug
specification a little.
Post by ***@yahoo.com [nuttx]