Discussion:
RISC-V Nuttx ... SUCCESS!
(too old to reply)
Ken Pettit pettitkd@gmail.com [nuttx]
2016-10-15 05:18:54 UTC
Permalink
SUCCESS!

On my RISC-V FPGA, I just now achieved:

NuttShell (NSH)
nsh>

And I am able to run multiple tasks, at least using a simple test like:

nsh> time "sleep 5" &
nsh> help

This properly displays the help usage and commands, followed by "5.0100
sec". Also, I ran the ostest example and it looks like all PASS
conditions there also. Now for some major cleanup, checking of file
header comments, and delay loop timing, etc.

Ken
Ramtin Amin keytwo@gmail.com [nuttx]
2016-10-15 08:54:10 UTC
Permalink
Congrats !!!!
really curious to see the code :p
Post by Ken Pettit ***@gmail.com [nuttx]
SUCCESS!
NuttShell (NSH)
nsh>
nsh> time "sleep 5" &
nsh> help
This properly displays the help usage and commands, followed by "5.0100
sec". Also, I ran the ostest example and it looks like all PASS
conditions there also. Now for some major cleanup, checking of file
header comments, and delay loop timing, etc.
Ken
Alan Carvalho de Assis acassis@gmail.com [nuttx]
2016-10-15 11:46:59 UTC
Permalink
Congratulations Ken!

It is an amazing achievement!

BR,

Alan
Post by Ken Pettit ***@gmail.com [nuttx]
SUCCESS!
NuttShell (NSH)
nsh>
nsh> time "sleep 5" &
nsh> help
This properly displays the help usage and commands, followed by "5.0100
sec". Also, I ran the ostest example and it looks like all PASS
conditions there also. Now for some major cleanup, checking of file
header comments, and delay loop timing, etc.
Ken
spudarnia@yahoo.com [nuttx]
2016-10-15 12:38:49 UTC
Permalink
Hi, Ken,
Post by Ken Pettit ***@gmail.com [nuttx]
SUCCESS!
NuttShell (NSH)
nsh>
nsh> time "sleep 5" &
nsh> help
Wow! That seemed like a very fast bring-up. But I bet it was not so fast from your point of view.

My Xtensa port is going very slowly. At this rate it will probably take me a month.
Post by Ken Pettit ***@gmail.com [nuttx]
This properly displays the help usage and commands, followed
by "5.0100 sec". ...
The 0.01 is one clock tick. Sleep always waits one clock tick longer than you request to assure that "at least" the requested time elapses (not at most). The time command also has an error of one clock tick. The real time is some time between 5.0000 and 5.0100.
Post by Ken Pettit ***@gmail.com [nuttx]
... Also, I ran the ostest example and it looks like all PASS
conditions there also. Now for some major cleanup, checking of file
header comments, and delay loop timing, etc.
The OS test is pretty good for this kind of thing. It really does exercise the core OS logic and certainly means that there are no major errors there.

I wish I had an easier to access PASS/FAIL indication from ostest. I usually just log the ostest results and do;

grep -I error ostest.log | grep -v nerrors=0

There is still some error counters that will be displayed but it is easy to assure that the counts are all zero.

Greg
spudarnia@yahoo.com [nuttx]
2016-10-16 15:55:15 UTC
Permalink
For those of you that have expressed an interest, Ken's RISC-V port is now available in the NuttX repository. Ken says that FPGA code will soon follow.


Greg
Ramtin Amin keytwo@gmail.com [nuttx]
2016-10-16 16:05:28 UTC
Permalink
Wow, great job.
thx
Post by ***@yahoo.com [nuttx]
For those of you that have expressed an interest, Ken's RISC-V port is now
available in the NuttX repository. Ken says that FPGA code will soon follow.
Greg
Ramtin Amin keytwo@gmail.com [nuttx]
2016-10-16 16:55:35 UTC
Permalink
hi Ken,

I know you derived your nanorv32 from a Picorv32.

I managed in the past to use a picorv32 in my soc:
https://github.com/cliffordwolf/picorv32/

How far is this picorv32 from your current soc, how much do you think would
need to be adapted to get it to work with this ?
Post by Ramtin Amin ***@gmail.com [nuttx]
Wow, great job.
thx
Post by ***@yahoo.com [nuttx]
For those of you that have expressed an interest, Ken's RISC-V port is
now available in the NuttX repository. Ken says that FPGA code will soon
follow.
Greg
spudarnia@yahoo.com [nuttx]
2016-11-23 23:35:55 UTC
Permalink
Crow supply project to develop a RISC-V chip: https://www.crowdsupply.com/onchip/open-v
Ken Pettit pettitkd@gmail.com [nuttx]
2016-11-24 00:36:52 UTC
Permalink
Hmm, 8K RAM. Wow, wonder what kind of programs they expect to run with
8K of combined code + data RAM!

I think I will spend Friday finishing the cleanup of my RISC-V FPGA
project (need to pull out a handful of non-releasable items still) and
get it posted to the world. The ASCIs I am developing have more like
256K SRAM for code and 128K for data, but then they are being devloped
in 14nm vs 130.

Perhaps I should talk to our CEO about doing a 40nm RISC-V Croud source
chip that is actually useful for something :)

Ken
Post by ***@yahoo.com [nuttx]
https://www.crowdsupply.com/onchip/open-v
spudarnia@yahoo.com [nuttx]
2016-11-29 22:59:52 UTC
Permalink
Yet another Crowd Supply RISC-V project: https://www.crowdsupply.com/sifive/hifive1
Ken Pettit pettitkd@gmail.com [nuttx]
2016-11-29 23:08:07 UTC
Permalink
This would be the first RISC-V chip developed by SiFive I believe.
SiFive was founded by the guys from Berkley who created the RISC-V. I
have been working with them on the RISC-V debug specification a little.

Ken
Post by ***@yahoo.com [nuttx]
https://www.crowdsupply.com/sifive/hifive1
franck gastel franckgastel@gmail.com [nuttx]
2016-11-30 00:18:18 UTC
Permalink
again I do not get the goal of making an asic out of a risc + a couple of
cores. what does it bring ?
This would be the first RISC-V chip developed by SiFive I believe. SiFive
was founded by the guys from Berkley who created the RISC-V. I have been
working with them on the RISC-V debug specification a little.
Ken
Yet another Crowd Supply RISC-V project: https://www.crowdsupply.com/
sifive/hifive1
Ken Pettit pettitkd@gmail.com [nuttx]
2016-11-30 01:04:43 UTC
Permalink
Developing an underpowered ASIC with a RISC-V and a couple of cores
(i.e. underpowered because no FLASH, limited RAM, limited peripherals)
really doesn't bring anything to the table in terms of a usable finished
product. Seems like more of a test platform. SiFive's business model is
that they can provide RISC-V cores for integration into a larger ASIC,
and the chip they developed is a test platform for demonstrating that
capability I believe. I'm not quite sure I understand SiFive's model
for making money though ... I think it *might* be as a consulting firm
to help companies develop custom extensions to the RISC-V ISA / core for
specialized hardware acceleration, etc.

Ken
Post by franck gastel ***@gmail.com [nuttx]
again I do not get the goal of making an asic out of a risc + a couple
of cores. what does it bring ?
This would be the first RISC-V chip developed by SiFive I
believe. SiFive was founded by the guys from Berkley who created
the RISC-V. I have been working with them on the RISC-V debug
specification a little.
Ken
Post by ***@yahoo.com [nuttx]
https://www.crowdsupply.com/sifive/hifive1
<https://www.crowdsupply.com/sifive/hifive1>
Michael Smith drziplok@gmail.com [nuttx]
2016-11-30 02:19:00 UTC
Permalink
It proves you can do it. This can be interesting to other folks that might want you to do it for them as part of a larger effort.

See e.g. PA Semi.

= Mike
again I do not get the goal of making an asic out of a risc + a couple of cores. what does it bring ?
This would be the first RISC-V chip developed by SiFive I believe. SiFive was founded by the guys from Berkley who created the RISC-V. I have been working with them on the RISC-V debug specification a little.
Ken
Yet another Crowd Supply RISC-V project: https://www.crowdsupply.com/sifive/hifive1 <https://www.crowdsupply.com/sifive/hifive1>
Loading...