[nuttx] hardfault, help analysing, where to start?

[[e-mail] [nuttx]]

i have a build of PX4 (nuttx 6.29 with some patches) with new lpc43xx chip files on 4337 chip running from flash (master vanilla nuttx has no such problem). This gives me a hardfault below if i stress nsh console (uart2) with some big output.

I read some threads but can't get a clue how to analyze the dump and where to look first:


1bXXX and 1aXXX addresses are flash. 100XXX - ram





Assertion failed at file:armv7-m/up_hardfault.c line: 184 task: hpwork
sp: 10001eb4
IRQ stack:
base: 10001f00
size: 000003fc
10001ea0: 1b02d961 1b03f07e 10001eb4 10005ed8 1a0312ab 1b03f600 000000b8 1b02d961
10001ec0: 00000010 10001f40 00000003 00000000 1a03721d 1a037209 1b02d93b 00000000
10001ee0: 1a0371f5 00000000 00000000 00000000 00000000 00000000 1a0314a5 10005d7c
sp: 10005e50
User stack:
base: 10005ed8
size: 00000f9c
10005e40: 00000000 00000000 00000000 1b02d587 10004900 00000000 005b8d7f 00000000
10005e60: 1a030f2e 00000000 00000000 00001388 00000000 00000005 10001994 00000000
10005e80: 00000000 00000000 00000000 1b02c359 00000000 00000000 00000000 004c4b40
10005ea0: 000002ff 00000000 00000000 1a030f2f 00000000 00000000 00000000 00000000
10005ec0: 00000000 1a030f41 00000000 1b02c2a5 00000000 00000000 ffffffff 00bdeb39
R0: ffffffff 00000000 00000016 00000000 00000000 00000000 00000000 00000000
R8: 100036d8 00000000 00000000 004c4b40 10001370 10005e50 1b02b20b 1b02d596
xPSR: 41000000 BASEPRI: 00000000 CONTROL: 00000000
EXC_RETURN: ffffffe9


ELF: https://www.dropbox.com/s/3dmq0np6s8fby51/firmware_nuttx?dl=0 https://www.dropbox.com/s/3dmq0np6s8fby51/firmware_nuttx?dl=0
config: defconfig https://www.dropbox.com/s/xzpapd3uvxwh731/defconfig?dl=0



https://www.dropbox.com/s/xzpapd3uvxwh731/defconfig?dl=0

defconfig https://www.dropbox.com/s/xzpapd3uvxwh731/defconfig?dl=0 Shared with Dropbox



View on www.dropbox.com https://www.dropbox.com/s/xzpapd3uvxwh731/defconfig?dl=0
Preview by Yahoo




Thnx,
Lok

[[e-mail] [nuttx]]

I have answered with question with the same parroted answer a dozen times or more.


Time for a Wiki page. I answered your question here: http://www.nuttx.org/doku.php?id=wiki:howtos:cortexm-hardfault http://www.nuttx.org/doku.php?id=wiki:howtos:cortexm-hardfault

[[e-mail] [nuttx]]

thank you, Greg
i'll try to dig into the problem. Just hoped that you can see a pattern of already fixed bug or something common...

Regards,
Lok

[[e-mail] [nuttx]]

i think it is interrupt disable problem on lpc43xx platform. I have CONFIG_ARMV7M_USEBASEPRI=y and last vanilla nuttx hardfaults. May be default interrupt priorities are not correct.

[[e-mail] [nuttx]]

Post by ***@yahoo.com [nuttx]
i think it is interrupt disable problem on lpc43xx platform. I have CONFIG_ARMV7M_USEBASEPRI=y and last vanilla nuttx hardfaults. May be default interrupt priorities are not correct.

That is possible. There were quite a few changes to LPC43xx committed recently. If the current build is broken, you might want do 'git bisect' to find the culprit.


Greg

[[e-mail] [nuttx]]

the problem is in nuttx\arch\arm\include\lpc43xx\chip.h

#define LPC43M4_SYSH_PRIORITY_STEP 0x10 - should be 0x20 - 3 last bits
#define LPC43M0_SYSH_PRIORITY_STEP 0x20 - should be 0x40 - 2 last bits

it looks like some other platforms have the same typo

[[e-mail] [nuttx]]

Thanks! You are right, that is a problem for LPC43xx if USE_BASEPRI is selected. Commit is a3e24a8adacdc9e8a3faa15c58ebfad7062685bb


I did not see any problems with any other architecture (other than some typos). The number of bits of priority vary between each processor family and, provided that the specified number of bits is correct, the definitions look okay to me.


Greg